1. Field of the Invention
The present invention generally relates to providing a dual gate metal oxide semiconductor field effect transistor (MOSFET) transistor and, more particularly, to providing a dual gate MOSFET having relatively thin epitaxially grown channels.
2. Background Description
Field Effect Transistor (FET) structures may include a single gate (a single channel) or a pair of gates, with double-gate versions providing the advantage of enabling shorter channels and thus a faster device to be produced. As gate lengths scale below 50 nm, FET scaling becomes limited by the finite depth of the gate control. Research has shown that placing gates on multiple sides of an FET channel results in improved FET performance in regard to short channel characteristics and off-current characteristics. Placing gates on multiple sides of an FET channel, provided the silicon is thin enough to be fully depleted, confines electric fields and charges much more tightly than in the standard FET in which the fields are free to penetrate deeply into an effectively infinite silicon substrate. The confinement possible with a fully depleted dual gate structure allows improved short channel effects and devices having gate lengths of 20-30 nm are possible. The inversion induced channels will be formed on both sides of the silicon and possibly across the entire channel which may increase saturation current. Other reported benefits include nearly ideal subthreshold slope, increased saturation current and reduced short-channel and floating body effects. Requirements generally are for a thin diffusion region in the range of 5-50 nm, and gate lengths down to 20-100 nm, with the gate length preferably being two to four times the diffusion length.
A number of horizontal double-gate FET structures, and particularly SOI double-gate FET structures, have been proposed. These structures typically require a bottom gate formed beneath the thin silicon body in addition to a conventional top gate. The fabrication of such structures is difficult because the top and bottom gates must be aligned to a tolerance beyond the accuracy of state of the art lithographical equipment and methods, and because self-aligning techniques are frustrated by the layers between the top and bottom gates.
In “Self-Aligned (Top and Bottom) Double-Gate MOSFET With a 25 nm Thick Silicon Channel”, by Hon Sum Philip et al., IEDM 97-427, IEEE 1997, a double-gated MOSFET is considered the most promising candidate for a Complementary Metal Oxide Semiconductor (CMOS) scaled to the ultimate limit of 20-30 nm gate length. Rigorous Monte Carlo device simulations and analytical calculations predicted continual improvement in device performance down to 20-30 nm gate length, provided the silicon channel thickness can be reduced to 10-25 nm and the gate oxide thickness is reduced to 2-3 nm. However, the alignment of the top and the bottom is crucial to high performance because a mis-alignment will cause extra gate to source/drain overlap capacitance as well as loss of current drive.
The following patents pertain to FETs, and particularly to the double-gated FETs.
U.S. Pat. No. 5,780,327, by Chu et. al. and entitled “Vertical Double-Gate Field Effect Transistor” describes a vertical double-gate field effect transistor, which includes an epitaxial channel layer and a drain layer arranged in a stack on a bulk or SOI substrate. The gate oxide is thermally grown on the sides of the stack using differential oxidation rates to minimize input capacitance problems. The gate wraps around one end of the stack, while contacts are formed on a second end. An etch-stop layer embedded in the second end of the stack enables contact to be made directly to the channel layer.
U.S. Pat. No. 5,773,331 by Solomon et. al. and entitled “Method for Making Single and Double Gate Field Effect Transistors With Sidewall Source-Drain Contacts” describes a method for making single-gate and double-gate field effect transistors having a sidewall drain contact. The channel of the FETs is raised with respect to the support structure underneath and the source and drain regions form an integral part of the channel.
U.S. Pat. No. 5,757,038 by Tiwari et. al. and entitled “Self-Aligned Dual Gate MOSFET with an Ultranarrow Channel” is directed to a self-aligned dual gate FET with an ultra thin channel of substantially uniform width formed by a self-aligned process. Selective etching or controlled oxidation is utilized between different materials to form a vertical channel extending between source and drain regions, having a thickness in the range from 2.5 nm to 100 nm.
U.S. Pat. No. 5,580,802 to Mayer et. al. and entitled “Silicon-on-Insulator Gate-All-Around MOSFET Fabrication Methods” describes an SOI gate-all-around (GAA) MOSFET which includes a source, channel and drain surrounded by a top gate, the latter of which also has application for other buried structures and is formed on a bottom gate dielectric which is formed on source, channel and drain semiconductor layers of an SOI wafer.
U.S. Pat. No. 5,308,999 to Gotou and entitled “MOS FET Having a Thin Film SOI Structure” describes a MOS FET having a thin film SOI structure in which the breakdown voltage of an MIS (Metal Insulator Semiconductor) FET having an SOI structure is improved by forming the gate electrode on the top surface and two side surfaces of a channel region of the SOI layer and by partially extending the gate electrode toward the inside under the bottom of the channel region such that the gate electrode is not completely connected.
U.S. Pat. No. 5,689,127 to Chu et. al. and entitled “Vertical Double-Gate Field Effect Transistor” describes a vertical double-gate FET that includes a source layer, an epitaxial channel layer and a drain layer arranged in a stack on a bulk or SOI substrate. The gate oxide is thermally grown on the sides of the stack using differential oxidation rates to minimize input capacitance problems. The gate wraps around one end of the stack, while contacts are formed on a second end. An etch-stop layer embedded in the second end of the stack enables contact to be made directly to the channel layer.
The lithographically defined gate is by far the simplest, but suffers from a number of disadvantages. First, definition of the gate may leave poly spacers on the side of the diffusions or may drive a required slope on the side of the diffusion, thereby resulting in a poorer quality and/or more poorly controlled device. Second, the slope of the poly inherently leads to difficulty in forming silicided gates, leading to slower device performance. Finally, the poly step height poses a difficult problem for lithographic definition, as we expect steps on the order of 100 nm-200 nm in a 50 nm design rule technology.
The key difficulties in fabricating double-gated FETs are achieving silicidation of thin diffusions or polysilicon with acceptable contact resistance, enabling fabrication of the wraparound gate without misalignment of the two gates, and fabrication of the narrow diffusions (ideally, 2-4 times smaller than the gate length).
Additional techniques for generating the dual-gated transistors include defining the gate lithographically with high step heights (see U.S. Pat. No. 4,996,574 to Shirasaki, entitled “MIS Transistor Structure for Increasing Conductance Between Source and Drain Regions”), forming a selective epitaxial growth which provides an “air-bridge” silicon structure (see Hon-Sum Philip Wong, International Electron Devices Meeting (IEDM) 1997, pg. 427), and forming wrap-around gates with vertical carrier transport (see H. Takato IEDM, 1988, pg. 222).
In summary, previous fabrication schemes have relied upon litographically defined silicon channels and long, confined lateral epitaxial growth. However, a lithographically defined channel cannot be formed with sufficiently close tolerances and even available tolerances cannot be maintained adequately to support near-optimal dual gate transistor performance in the above approaches. Further, techniques using lateral current flow with FET widths defined laterally suffer from difficulty in aligning the top and bottom gates even though thickness of silicon can be tightly controlled.
U.S. patent application Ser. No. 09/526,857, by James W. Adkisson, John A. Bracchitta, John J. Ellis-Monaghan, Jerome B. Lasky, Kirk D. Peterson and Jed H Rankin, filed on Mar. 16, 2000, and incorporated by reference above, entitled “Double Planar Gated SOI MOSFET Structure” describes a method to create the double gate transistor, assuming the channel width can be made small enough.